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1 datasheet power factor correction controllers isl6731a, isl6731b the isl6731a and isl6731b are active power factor correction (pfc) controller ics that use a boost topology. the controllers are suitable for ac /dc power systems up to 2kw and over the universal line input. the isl6731a and isl6731b operate in continuous current mode (ccm). accurate input current shaping is achieved with a current error amplifier. a patent pending breakthrough negative capacitance technolo gy minimizes zero crossing distortion and reduces the magnetic components size. the small external components result in lower design cost without sacrificing performance. the internally clamped 12.5v gate driver delivers 1.5a peak current to the external power mosfet. the isl6731a and isl6731b provide a highly reliable system that is fully protected. protection features include cycle-by-cycle overcurrent, over power limit, over-temperature, input brownout, output overvoltage and undervoltage protection. the isl6731a and isl6731b provide excellent power efficiency and transitions into a power saving skip mode during light load conditions, thus improving efficiency automatically. the isl6731a and isl6731b can be shut down by pulling the fb pin below 0.5v or grounding the bo pin. two switching frequency options are provided. the isl6731b switches at 62khz, and the isl6731a switches at 124khz. related literature ? an1884 , "isl6731aeval1z and isl6731beval1z: boost ccm pfc for 300w universal input adaptors" ? an1885 , ?isl6731aeval2z and isl6731beval2z: high performance boost ccm pfc front end for server power applications? features ? reduced component size requirements - enables smaller, thinner ac/dc adapters - choke and cap size can be reduced - lower cost of materials ? excellent power factor and thd over line and load - ccm mode with negative capacitance generator for smaller emi filter and improved performance - built-in current amplifier with flexibility of gain change ?better light-load efficiency - automatic pulse skipping with programmable threshold - programmable or automatic shutdown ? highly reliable design - cycle-by-cycle current limit - input average power limit - ovp and otp protection - input brownout protection ?small 14 ld soic package applications ? desktop computer ac/dc adaptor ? laptop computer ac/dc adaptor ?tv ac/dc power supply ?ac/dc brick converters figure 1. typical application figure 2. pfc efficiency + isl6731a vcc isen icomp vin gate gnd fb bo vreg comp v line v out v i skip ovp output power (%) efficiency (%) isl6731a, non-skip isl6731a, skip 100 95 60 65 70 90 85 80 75 0 20 40 60 80 100 february 13, 2015 fn8582.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl6731a, isl6731b 2 fn8582.1 february 13, 2015 submit document feedback pin configuration isl6731a, isl6731b (14 ld soic) top view 11 12 14 13 4 3 2 1 nc gnd isen icomp gate vcc vreg nc 10 5 vin skip 9 8 6 7 bo ovp comp fb pin descriptions pin # i/o symbol description 1, 13 - nc not connected. must be floating. 2 - gnd ground pin. all voltage levels refer to this pin. 3 i isen current sense pin. the current through this pin is proportional to the inductor current. 4 i/o icomp current error amplifier output pin. 5 i vin input voltage sense. this pin provides the reference voltage to shape inductor current. conn ect this pin to a resistor div ider from the rectified input voltage. the resistor divider ratio is used to adjust the phase lag between input voltage and the input current. the phase lag is required to compen sate the phase lead generated by the emi filter. 6 i/o bo this pin should be decoupled to gnd with a minimum 0.1f ceramic capacitor. the bo pin is a voltage follower, which will follow the dc voltage of the vin pin. the bo pin is internally tied to gnd through a resistor r is . the decoupling capacitor provides ripple filtering. when the voltage at the bo pin (v bo ) drops below brownout voltage threshold, the controller enters shutdown mode and the gate drive is disabled. the bo pi n will be disabled when the fb pin drops below the enabling threshold. 7 i ovp overvoltage protection pin. connect this pin to a resistor divider from the output. the resi stor divider sets the ovp set point. when the ovp pin voltage exceeds 104.5% of the reference voltage v ref , ovp is triggered and the gate drive is disabled. 8 i/o comp output of the error amplifier. the voltage of the comp pin sets the input power. during start-up, a small charge curren t will slowly ramp up the voltage of the comp pin. 9 i fb voltage feedback pin. connect this pin to a resistor divider from the output. the resistor divider sets the output voltage. when the fb pin voltage exceeds 104% of v ref , ovp is triggered and gate drive is disabled. when the fb pin drops below 10% of v ref , the device is put into shutdown mode. there is an inte rnal pull-down current source for open loop protection. 10 i/o skip this pin has dual functions. conn ecting this pin to ground disables the light load skip function. an internal 20 a current sources out of this pin. connect a resistor from this pin to the ground to set the average power trip point. the converter exits the skip mode when either the vfb drops below 88% of v ref , or the isen current goes above 29 a. 11 - vreg output of internal regulator. the voltage having a 2% to lerance over line, load and operating temperature. bypass to gn d with a 47nf low esr capacitor. vreg can source up to 10ma. this pin is not recommended for usage other than bypass. 12 i vcc power supply pin. the vcc pin should be decoupled to gnd with a minimum 0.1f ceramic capacitor. 14 o gate push-pull gate drive for the external mosfet. output voltag e is clamped at 12.5v. this pin provides typically 2a sink an d 1.5a source capability.
isl6731a, isl6731b 3 fn8582.1 february 13, 2015 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6731AFBZ isl 6731afbz -40 to +125 14 ld soic m14.15 isl6731bfbz isl 6731bfbz -40 to +125 14 ld soic m14.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6731a , isl6731b . for more information on msl please see techbrief tb363 . table 1. key differences in family of isl6731 version isl6731a isl6731b switching frequency 124khz 62khz
isl6731a, isl6731b 4 fn8582.1 february 13, 2015 submit document feedback block diagram fb comp gate pwm vcc control logic vin isen oscillator comp gnd otp vcc bo i fb r sen r is icomp i ref ceq gen. current mirror overpower limit soft-start enable vref skip 20a skip clamp skip 2:1 0.25 vin bo 2 ---------------------------- c o m p b q 1 c out v out l comp-1v r cs v cs r is i isen 2 --------------------------------- - = c f1 c f2 v line c f3 emi choke uvlo r fb1 r fb2 l m r in2 c bo r in1 d i cs i oc 2 ------------- - > i cs compb d f1 d f2 c reg linear regulator vreg v i gmi gmv ovp r ov2 r ov1 l f vro1 vro2
isl6731a, isl6731b 5 fn8582.1 february 13, 2015 submit document feedback application schematics typical 300w application schematic 0.22 r28 tp7 dnp 0.22 r27 r3 2m r1 2m d2 c3d04060a 2 1 tp12 gate1 1u c9 - + db1 gbu806 l1 0u r19 42.2k c35 2.2n c36 2.2n c20 47n c19 0.1 vcc c17 1n dnp p4 p1 8a f1 q2 2n7002 dnp 1 3 2 10k r20 dnp c21 0.1 25k r21 dnp vcc dc+ p7 p6 gnd vcc c12 dnp c26 2.2n c15 150n 3.3m r6 s1m d7 3.3m r10 s1m d8 3.3v dz1 q1 spp20n60c3 1 3 2 c5 2.2n 470k r11 c14 470n r17 0 5.76k r13 c3 68 0 n uvlo logic pwm gm gm 2.5v c skip opl 2:1 + - otp i mirror ceq gen icomp gate gnd fb comp bo vin isen vcc i* 4*bo*bo i*= vin*c lin.reg. vreg skip ovp u1 isl6731a/b 9 14 2 12 3 4 5 6 8 11 7 10 1 13 c6 2.2n c16 100n 51k r4 r2 2.2 l3 2.2m 4 3 1 2 270u c1 450v 1 2 62k r18 c18 1u 0.22 r5 3k r9 c8 220n c13 47p 470k r8 vreg 3.3m r24 c23 1n 3.3m r23 r25 42.2k vout gnd fb bo comp gate icomp isen vin c22 470n tp11 dnp ovp 69.8k r22 pe ac2 ac1 l2 1.5m d1 in5406 tp2 tp1 tp3 tp4 tp5 390v universal input 90~265vac tp9 tp10 p5 1u c7 p2 p3 p8 dnp p9 dnp c10 6.8n c11 1n tp6 r14 30k tp8 dnp rv1 mov /dnp l4 2.2m 4 3 1 2 c2 470n r26 49.9
isl6731a, isl6731b 6 fn8582.1 february 13, 2015 submit document feedback typical 85w application schematic application schematics (continued) 1u c9 r19 42.2k c20 47n vcc p6 p7 gnd vcc c15 100n r6 3.3m r10 3.3m 3.3v dz1 r11 470k c14 470n r13 5.76k c16 1n r18 68k c18 2.2u r9 2.1k c8 220n c13 220p r8 470k r22 69.8k r1 2m r3 2m l4 cmt1 4 3 1 2 p4 p1 s1m d7 s1m d8 ac2 ac1 f1 3.15a universal input 90~265vac c2 100n uvlo logic pwm gm gm 2.5v c skip opl 2:1 + - otp i mirror ceq gen icomp gate gnd fb comp bo vin isen vcc i* 4*bo*bo i*= vin*c lin.reg. vreg skip ovp u1 isl6731a 9 14 2 12 3 4 5 6 8 11 7 10 1 13 1u c7 c11 470p c10 6.8n r14 5.36k r28 0.22 s3kb-tp d4 s3kb-tp d5 s3kb-tp d6 s3kb-tp d3 d2 c3d04060e 3 1 s3kb-tp d1 l2 2.2m dc+ q1 ipp60r600c6 1 3 2 c3 330n r4 51k r2 2.2 56u c1 450v 1 2 vout tp9 390v p2 tp10 p3
isl6731a, isl6731b 7 fn8582.1 february 13, 2015 submit document feedback absolute maximum rating s thermal information vcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v gate to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +18v vin, bo, isen, fb, ovp, icomp, skip, vreg and comp to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.3v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd-c101e) . . . . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma recommended operating conditions vcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v to + 20v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical) ? ja (c/w) ? jc (c/w) soic package ( notes 4 , 5 ) . . . . . . . . . . . . . 77 38 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply across th e operating temperature range, -40c to +125c . parameter symbol test conditions min ( note 8 )typ max ( note 8 )units v cc supply current start-up current i start v fb = 1v, v cc < v cc (on) 73 106 139 a standby current i stdn v fb = gnd, v cc > v cc (on) 179 237 295 a skip mode current i ccskip v fb = 2.5v, comp = skip*0.25 +1v 580 690 850 a operating current ( note 6 )i cc gate is floating 3.0 3.7 4.5 ma vcc uvlo uvlo rising threshold v cc(on) 91011v uvlo falling threshold v cc(off) 6.7 7.5 8.3 v uvlo threshold hysteresis v cc(hys) 2.5 v regulator voltage vreg overall accuracy v reg i reg = 0 to -10ma, v cc = 15v, load capacitor = 47nf 5.1 5.4 5.6 v current limit 30 50 70 ma pwm converters maximum duty cycle f sw = 124khz for isl6731a and f sw = 62khz for isl6731b 94.8 96.5 % oscillator free running frequency, isl6731a t a = -40c to +125c, v in = 0.6v 95.5 107 117 khz free running frequency, isl6731a t a = -40c to +125c, v in = 2.5v 111 125 138 khz free running frequency, isl6731b t a = -40c to +125c, v in = 0.6v 43.5 54 63.7 khz free running frequency, isl6731b t a = -40c to +125c, v in = 2.5v 56.5 64 70.7 khz pwm ramp amplitude v m 1.33 1.46 1.59 v
isl6731a, isl6731b 8 fn8582.1 february 13, 2015 submit document feedback gate driver gate drive pull-down resistance v cc = 15v, i gate = 15ma 2.33 4.46 gate drive pull-up voltage drop v cc = 9v, i gate = 15ma 0.15 0.3 0.45 v gate drive max. sourcing/sinking current 1.5 a rise time c o = 2.2nf, v cc = 15v, gate voltage rise time from 10% to 90% of v gc 34 62 ns fall time c o = 2.2nf, v cc = 15v, gate voltage fall time from 10% to 90% of v gc 34 57 ns gate clamp voltage v gc 10.5 12 13.5 v voltage reference reference voltage v ref 2.48 2.5 2.52 v feedback pin pull-down current i fb 65 na rising threshold to enable converter fb_en 280 300 320 mv falling threshold to disable converter fb_dis 190 202 214 mv enable hysteresis fb_hys 100 mv voltage error amplifier error amp transconductance gmv 50 77 104 a/v isource/sink 13 a comp offset voltage v comp_off 0.95 1.01 1.07 v comp soft-start enable voltage v comp_en 0.58 0.64 0.75 v input voltage sensing vin leakage current 9na multiplier gain gmul comp = 2.5v, v in = 1.0v, bo = 1.0v, i sen = 50a 0.196 0.25 0.296 v/v current error amplifier current dc gain a idc ? i icomp / ? i isen 1.6 1.9 2.2 a/a error amp transconductance gmi i icomp = 20a 205 268 331 a/v icomp source/sink current ( note 7 ) 60 a current sensing input offset -3 2 7 mv light load efficiency enhancement and overpower protection skip current reference ( note 7 )i skip v skip = 2v -23 -20 -17 a skip falling threshold v skip_thf 450 498 550 mv skip rasing threshold v skip_thr 570 616 690 mv comp upper limit v cul 3.53 3.85 4.17 v comp valid range v cul -1v 2.5 2.83 3.16 v fb exit threshold voltage v fb_exit fraction of v ref , i isen = 0a 87 88 89 % isen exit threshold current i sen_exit v fb = 2.5v -38 -29 -20 a electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply across th e operating temperature range, -40c to +125c . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )units
isl6731a, isl6731b 9 fn8582.1 february 13, 2015 submit document feedback brownout detection brownout rising threshold v bo_r 478 494 510 mv brownout falling threshold v bo_f 387 401 415 mv overvoltage protection overvoltage protection, fb pin v ro1 fraction of v ref ; ~1s noise filter 103 104.1 106 % overvoltage protection, ovp pin v ro2 fraction of v ref ; ~1s noise filter 103 104.2 106 % overcurrent protection overcurrent threshold i oc -197 -177 -159 a thermal shutdown shutdown temperature ( note 7 ) 160 c thermal shutdown hysteresis ( note 7 ) 25 c notes: 6. this is the v cc current consumed when the device is active but not switching. does not include gate drive current. 7. limits should be considered typical and are not production tested. 8. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply across th e operating temperature range, -40c to +125c . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )units typical performance curves figure 3. feedback accuracy figure 4. f sw vs temperature, v cc = 15v temperature (c) vfb normalized (%) 99.50 99.75 100.00 100.25 100.50 -40 -20 0 20 40 60 80 100 120 140 f sw normalized (%) 99.0 99.5 100.0 101.0 v in = 0.6v v in = 2.5v temperature (c) -40 -20 0 20 40 60 80 100 120 140 100.5
isl6731a, isl6731b 10 fn8582.1 february 13, 2015 submit document feedback figure 5. a idc vs temperature figure 6. f sw vs v in, t a = +25 c figure 7. uvlo thresholds vs temperature figure 8. v cc supply current vs temperature figure 9. gate drive timing vs temperature (load = 2.2nf) typical performance curves (continued) temperature (c) 97 98 99 100 101 -40 -20 0 20 40 60 80 100 120 140 a idc normalized (%) 75 80 85 90 95 100 105 f sw normalized (%) v in (v) 0 0.51.01.52.02.53.0 98 99 100 101 102 -40 -20 0 20 40 60 80 100 120 140 up down hysteresis temperature (c) uvlo threshold normalized (%) threshold threshold 98 99 100 101 102 -40 -20 0 20 40 60 80 100 120 140 i cc temperature (c) v cc current normalized (%) (gate floating) i start temperature (c) gate drive timing normalized (%) 96 98 100 102 104 106 108 110 112 -40 -20 0 20 40 60 80 100 120 140 rise time fall time
isl6731a, isl6731b 11 fn8582.1 february 13, 2015 submit document feedback functional description vcc undervoltage lockout (uvlo) the isl6731a and isl6731b st art automatically once the voltage at vcc exceeds the uvlo threshold. shutdown when the vfb pin is below 0.2v, the controller is disabled and the pwm output driver is tri-stated. when disabled, the ic power will be reduced. during shutdown, the comp pin is discharged to gnd and the controller is disabled. the over-temperature protection (otp) is still alive to prevent the controller from starting up in a high te mperature ambient condition. in the event that the fb pin is disconnected from the feedback resistors, the fb pin is pulled to ground by an internal current source i fb . when the fb pin voltage drops below 0.2v, the gate driver is disabled. the isl6731a or isl6731b enters shutdown mode. soft-start the comp pin is released once the soft-start operation begins. a 13a current sources out to the rc network connected from the comp pin until the fb pin voltage reaches 90% of the reference voltage. switching is inhibited when the comp pin voltage is below 1v. when the comp pin reaches 1v, the current error amplifier and the gate driver are activated and the converter starts switching. during uvlo, brownout and shutdown, the comp is pulled to the ground. input voltage sensing the vin pin is needed to sense the rectified input voltage. the sensed semi-sinusoidal wavefo rm is needed to shape the inductor current, which helps achieves unity power factor. at the same time, the voltage on the vin pin is used to generate the negative capacitive element at the input. this will cancel the input filter capacitor, c f . canceling the effect of c f will increase the displacement power factor an d alleviate the zero crossing distortion, which is related to the distortion power factor. the bo pin also utilizes the vi n resistor divider for voltage sensing. set the resistor divide r ratio to satisfy the brownout requirement. first, calculate the resistor divider ratio, k bo . where v f is the forward voltage drop of the bridge rectifier and the voltage drop of d f1; d f2 . then, select the r in2 based on the highest reasonable resistance value. then select the r in1 based upon the desirable minimum rms value of the line voltage for the pfc operation. inductor current sensing the current sensing of the conver ter has two purposes. one is to force the inductor current to track the input semi-sinusoidal waveform. the other purpose is for overcurrent protection. refer to figure 11 for the current sensing scheme. the sensed current i cs is in proportion to the inductor current, i l as described in equation 3 : where: r cs is the current sensing resistor with low value in the return path to the bridge rectifier. r sen is the current scaling resistor connected between isen to the r cs . a high value r cs renders more accurate current sensing. it is recommended to use the r cs to render 120mv peak voltage at the maximum line voltage during full load condition. where ?? is the efficiency of the converter at the maximum line input with full load. figure 10. input voltage sensing schematic bo r in1 c bo vin c f2 v line c f3 emi choke l m d f1 d f2 r in2 k bo v bormax v rmsmin 2v f C ------------------------------------------- = (eq. 1) r in1 k bo 1k C bo --------------------- r in2 ? = (eq. 2) i cs 1 2 -- - r cs r sen --------------- - i l ?? = (eq. 3) figure 11. inductor current sensing scheme q1 cout vout l cf1 v i rcs isen rsen current mirror 2:1 i cs 0.5 i oc > i cs r cs 120mv v rmsmax ? ?? 2p omax ? ------------------------------------------------------------- ? (eq. 4)
isl6731a, isl6731b 12 fn8582.1 february 13, 2015 submit document feedback since the r cs sees the average input current, high value r cs generates high power dissipation on the r cs . use a reasonable r cs according to the resistor power rating. the worst-case power dissipation occurs at the input low line when input current is at its maximum. power dissipation by the resistor is: where: i rmsmax is the maximum input rms current at the minimum input line voltage, v rmsmin . select the r sen according to the peak current limit requirement. the resistor is sized for an overload current 25% more than the peak inductor peak current. negative input capacitor generation (patent pending) the patent pending negative capa citor generation capability of isl6731a and isl6731b allow the capacitor c f2 to be moved from before the bridge rectifier ( figure 12 ) to after the bridge rectifier ( figure 13 ). thus, a smaller, lower cost c f2 can be used. the change in topology reduces the size of the emi filter. furthermore, c f1 can be increased thus de creasing the size of l f ( figure 13 ). for applications where the output power is above 500w, the negative capacitance helps to improve the power factor dramatically. refer to table 2 for the recommended filtering capacitor to be placed after the bridge rectifier, c f1 . additional c f1 may be used to accommodate the use of small boost inductor or to eliminate the differential mode filter inductor as long as the equipment meets the power factor or goal. the equivalent negative capacito r is a function of the input voltage divider ratio, k bo , the current sensing gain and current compensation error integration gain. adjusting the negative ceq can be achieved by adjusting the current compensation network. frequency modulation the isl6731a and isl6731b can furt her reduce emi filter size by lowering the differential noise power density. the reduction is achieved by switching frequency modulation. the frequency varies with the vin pin. the switching frequency reaches the peak value when the vin pin voltage is 2v as shown in figure 6 . the peak value of isl6731a is 124khz, and the isl6731b is 62khz. output voltage regulation the output voltage is sensed through a resistor divider. the middle point of the resistor divider is fed to the fb pin. the resistor divider ratio sets the output voltage. the transconductance error amplifier generates a current in proportion to the difference between the fb pin and the 2.5v internal reference. the pfc is stabilized by the compensation network that is connected from the comp pin to the ground. the voltage of the comp sets the input average power by determining the amplitude of the current reference. to keep the harmonic distortion to a minimu m, it is desirable to set the control bandwidth much lower than twice of the line frequency. the recommended voltage loop bandwidth is 10hz. during start-up, the compensation capacitors and the charging current from the error amplifier sets the input power increase rate. thus, soft-start is achieved. the comp is discharged during shutdown and fault conditions. light load efficiency enhancement for pc, adaptor and tv applications, it is desirable to achieve high efficiency at light load conditions and low standby current. the isl6731a and isl6731b can enter light load skip mode automatically. the skip mode trigger threshold is adjustable by the skip pin. a 20a current source out of the skip pin sets the voltage on the pin via a resistor connected between the pin and ground. connecting this pin to grou nd disables the light load skip function. the voltage error amplifier output, comp, is an indicator of the average input power level. the controller compares the v(comp) and v(skip). if v(comp)-1v is less than v(skip)*0.25, the pfc controller stops gate switching and the comp pin voltage is clamped to v(skip)+0.6v. the controller exits skip mode when v fb drops to 88% (typical) of the reference voltage or when the sensed returned current exceeds 29a. figure 12. typical pfc input filter circuit figure 13. low cost pfc input filter circuit table 2. recommended filtering capacitor c f1 p o < 100w 100w < p o < 500w p o > 500w typical c(f)/100w 0.68 0.33 0.22 p rcs i rmsmax ?? 2 r cs ? = (eq. 5) c f1 c f2 v line c f3 emi choke l m bridge recfifier l f c f1 c f2 v line c f3 emi choke l m bridge recfifier l f
isl6731a, isl6731b 13 fn8582.1 february 13, 2015 submit document feedback protection circuits input brownout, bo protection brownout occurs when there is a drop in the line voltage. the bo pin is a dual function pin. the bo pin detects the brownout condition and shuts down the gate driver and controller. during normal operation, the bo pin is used to compensate the effect of the input line voltage change on the voltage loop. to keep the harmonic distortion low, the corner frequency formed by the r bo and c bo should be lower than 6hz. the bo pin is the output of the average voltage of the rectified voltage. the pfc controller is turned off when the bo pin drops below 0.4v. this protects the pfc power stage to enable operation at or below brownout condition for long periods of time. the controller resumes operation when the bo pin returns to 0.5v. the bo pin is usually connected to gnd through a capacitor, c bo . to avoid distortion on the vin pin, select c bo so that: overcurrent protection the peak current limit function prevents the inductor from saturation. the gate dr iver turns off when the current goes above the current limit set point. overpower protection the overpower protection is implemented by limiting the comp pin voltage higher than 3.85v (typical). overvoltage protection if the voltage on the fb pin exceeds the reference voltage v ref by about 4%, the gate driver is turned off. if the voltage on the ovp pin exceeds the v ref by about 4.5%, the gate driver is turned off. the controller resumes normal op eration after both ovp and fb pin drops below v ref . over-temperature protection the isl6731a and isl6731b are protected against over-temperature conditions. when the junction temperature exceeds +160c, the pwm shuts down. normal operation is resumed when the junction temp erature decreases below +135c. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or sing le point grounding. figure 14 shows the critical power components; q 1 , d and c out . to minimize the voltage oversh oot, the interconnecting wires indicated by heavy lines should be part of the ground or the power plane in a printed circuit board. the components shown in figure 14 should be located as close together as possible. please note that the capacitors c vcc and c o each represent numerous physical capacitors. locate the isl6731a or isl6731b within 2 inches of the mosfet, q 1 . the circuit traces for the mosfets? gate and source connections fr om the isl6731a and isl6731b must be sized to handle up to 1.5a peak current. component selection guidelines a 300w, universal input, pfc converter design is provided for demonstration. the design method is for a continuous current mode power factor correction boost converter with the isl6731b. the switchin g frequency is 62khz. tables 3 shows the design parameters. boost inductor selection first, calculate the maximum input rms current, i inmax. where ?? is the converter efficiency at v rmsmin . pf is the power factor at v rmsmin. assuming the current is sinusoidal and the peak-to-peak ripple at line is 40%. c bo 0.22 ? f ? (eq. 6) table 3. converter design parameters parameter conditions min typ max unit v line 90 115/230 265 v ac f line 47 63 hz p omax maximum output power 300 w t hold hold up time 20 ms efficiency v line = 115v ac 92 % figure 14. critical current power components q 1 c out l d gate vcc c vcc i inmax p omax ? v ? rmsmin ----------------------------------- = (eq. 7) i inmax 300w 0.92 90v ? ---------------------------- 3.62a == (eq. 8)
isl6731a, isl6731b 14 fn8582.1 february 13, 2015 submit document feedback the boost inductor, l bst , is given in equations 9 and 10 : choose inductance of 1.5mh, consider the r will decrease at high current for a powder core indu ctor. the peak current of the inductor is the sum of the averag e peak inductor current and half of the peak-to-peak ripple curren t. select and design the boost inductor as given by equation 11 . the isl6731a and isl6731b provides peak current limit function that can prevent the boost inductor saturation. assuming 25% margin is given to the ocp threshold, select and design the boost inductor with saturation current given by equation 11 with 25% margin. input rectifier the maximum average input current is calculated: select the bridge diode using equation 15 and sufficient reverse breakdown voltage. assuming the forward voltage, v f,br , is 1v across each rectifier diode. the power loss of the rectifier bridge can be calculated: input capacitor selection refer to table 2 for the recommended input filter capacitor value. this is the recommended capacito r used after the diode bridge. for better power factor, less capacitance can be used. to lower the input filter inductor size, more capacitance can be used. one 0.68f capacitors is used for c f1 . boost diode selection the boost diode loss is determined by the diode forward voltage drop, v f and the output average current. the maximum output current is: the forward power loss on the diode is: the cree c3d10060a sic schottky diode is selected. the reverse recovery loss on the diode can be calculated. the q rr is found from the diode datasheet. q rr = 25nc. the reverse recover loss on the diode can be estimated: the total power loss on the diode is: mosfet power dissipation the power dissipation on the mosfet is from two different types of losses; the conduction loss and the switching loss. for the mosfet, the worst case is at minimum line input voltage. first, the drain-to-source rms current is calculated: the mosfet, spp20n60c3 is selected. the switching loss of the mosfet consists of three parts: the turn-on loss, the turn-off loss and the diode reverse recovery loss. from the mosfet datasheet, the typical switching losses curves are provided. when r g = 3.6 , i d = 6a, e on = 0.013mj, e off = 0.020mj. the switching loss due to transition is calculated: the loss caused by c oss can be estimated as: from the mosfet datasheet, the c oss =197pf when v out = 390v. l bst 2v rmsmin 0.4 f sw 2 ? ? i inmax ? --------------------------------------------------------------- - 1 2v rmsmin ? v out --------------------------------------- C ?? ?? ?? ? ? (eq. 9) l bst 90v 0.4 64khz 3.62 ? a ? ----------------------------------------------------- - 1 290v ? 390v ----------------------- - C ?? ?? ? ? 654 ? h = (eq. 10) i lpeak 2i ? inmax 1 ? i 2 ----- + ?? ?? ? = (eq. 11) i lpeak 23.88a ? 1 1.786a 2 ------------------ - + ?? ?? ? 6.017a == (eq. 12) i inave max ?? 22 ? i inmax ? ? ------------------------------------------ = (eq. 13) i inave max ?? 22 ? 3.62a ? ? -------------------------------------- 3.3a == (eq. 14) p br 2v fbr ? ? i inave max ?? ? = (eq. 15) p br 21v ? 3.3a ? 6.524w == (eq. 16) c f1 300w 0.33 100 ----------- ? 0.99 ? f == (eq. 17) i out max ?? p omax v out -------------------- = (eq. 18) i out max ?? 300w 390v --------------- - 0.77a == (eq. 19) p fd i out max ?? v f ? = (eq. 20) p fd 0.77a 0.9v ? 0.692w == (eq. 21) p rrd 1 4 -- - q ? rr v out ? f ? sw = (eq. 22) p rrd 1 4 -- - 25nc ? 390v ? 62khz ? 0.156w == (eq. 23) p d p fd p rrd + 0.692 0.156 + ?? w 0.848w == = (eq. 24) i ds max ?? i inmax 1 82 3 ? ---------- - v rmsmin v out ------------------------- - ? C = (eq. 25) i ds max ?? 3.623a 1 82 3 ? ---------- - 90v 390v ------------- - ? C 3.081a == (eq. 26) p cond i ds max ?? 2 r ds on ?? ? = (eq. 27) p cond 3.3a 2 0.285 ? ? 2.71w == (eq. 28) p sw e on e off + ?? f ? sw = (eq. 29) p sw 0.013mj 0.020mj + ?? 64khz ? 2.09w == (eq. 30) p oss 2 3 -- - c oss v out 2 ? f ? sw = (eq. 31) p oss 2 3 -- - 197pf 390v 2 ? 64khz ? 1.28w == (eq. 32)
isl6731a, isl6731b 15 fn8582.1 february 13, 2015 submit document feedback the total loss on the mosfet output capacitor selection the output capacitor, c o , is required to hold the output above 300v during one line cycle. for capacitors with 20% tolerance, the tolerance should be taken into consideration. thus, the output capacitance should be greater than: calculate the ripple rms current through the capacitor: select the proper capacitor according to the hold time and ripple rms current requirement. the actual capacitance is 270f. it is important to make sure th e output peak-to-peak ripple is less than the minimum ovp thresh old as specified in the table on ? electrical specifications ? on page 7 . the esr of the capacitor at 2 times of line frequency is found in the capacitor datasheet. the esr is 737m at 100hz. the minimum ovp threshold is 103% of the nominal output value. the maximum output peak-to-peak ripple should be less than 6% of the nominal value, which is 23.4v p-p . current sensing resistors please refer to equation 4 for calculation of the current sensing resistor r cs . while a large r cs renders better current sensing accuracy, larger r cs also incurs higher power dissipation. select three 0.22 resistors in parallel as r cs . the maximum power dissipation on the r cs occurs at low line and full load condition. the maximum power dissipation is calculated: the resistor, r sen sets the overcurrent protection limit. from equation 3 , r sen should be greater than: where |x| stands for the abs(x) function, i oc is the overcurrent threshold. select r sen from available standard value resistors, the selected r sen is 3k ? current loop compensation the input current shaping is achieved by comparing the sensed current signal to the sensed inpu t voltage signal. the current error amplifier (gmi), together with th e current compensation network, adjusts the duty cycle so that the inductor current traces the sensed rectified voltage. thus, unity power factor is achieved. the compensation network consists of the trans-conductance error amplifier (gmi) and the impedance network (z icomp) . the goal of the compensation networ k is to provide a closed loop transfer function with the suff icient 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the open loop phase at f 0db and 180. the following equations relate the compensation network?s poles, zeros and gain to the components (r ic , c ic and c ip ) in figure 15. p cond p sw p + oss + 2.71w 2.09w 1.28w ++ 6.08w == (eq. 33) c o 2t hold p ?? omax v out 2 v hold 2 C ---------------------------------------------------- 1 10.2 C ----------------- ? ? (eq. 34) c o 2 20ms 300w ?? 390 ?? 2 300v ?? 2 C ---------------------------------------------- 1.25 242 ? f = ? ? (eq. 35) i corms max ?? i out max ?? 82 3 ? ---------- - v out v rmsmin ------------------------- - ? 1 C = (eq. 36) i corms max ?? 0.77a 82 3 ? ---------- - 390v 90v ------------- - ? 1 C 1.577a == (eq. 37) v opp i out max ?? 4 ? f line c o esr ?? ?? 2 1 + 2 ? f line ?? c o 0.8 ?? --------------------------------------------------------------- -------- ? = (eq. 38) v opp 0.77a 4 ? 50hz 270 ? f0.77 ? ?? ? ?? 2 1 + 2 ? 50hz ? ?? 270 ? f0.8 ?? --------------------------------------------------------------- ---------------------------- - ? 9.6v == (eq. 39) r cs 120mv 265v 0.92 ?? 2300w ? ------------------------------------------------------ - ? 0.069 ? = (eq. 40) r cs 0.073 ? = (eq. 41) p rcsmax i inmax 2 r ? cs = (eq. 42) p rcsmax 3.623a 2 0.073 ? ? 0.963w == (eq. 43) r sen r cs i lpeak 10.2 + ?? ? ? 20.5i oc ? --------------------------------------------------------------- - - ? (eq. 44) r sen 0.073 ? 6.017a 1.2 ? ? 290 ? a ? ---------------------------------------------------------- - ? 2.9k ? = (eq. 45) figure 15. inductor current sensing scheme q 1 c out v out l c f1 r cs isen r sen current mirror 2:1 i cs icomp i ref gmi r ic c ic r is c ip v i
isl6731a, isl6731b 16 fn8582.1 february 13, 2015 submit document feedback use the following guidelines for locating the poles and zeros of the compensation network. near the crossover frequency, th e transfer function from duty cycle to inductor current is well approximated by equation 48 : the compensation gain uses external impedance networks as shown in figure 15 , g ci (s) is given by: the current gain and modulation gain gsm is: where vm is the amplitude of the pwm carrier. the open loop gain of the current loop is: it is recommended to set the crossover frequency, f c from 1/10 to 1/6 of the switching frequenc y with a phase margin of 60. a high frequency pole, f p, is set at 1/2 of th e switching frequency for ripple filtering. in this example, we set the f c at 14khz. where ? m is the phase margin, which is 20. f p = 6khz. this is an aggressive example to fulf ill a tight thd for light load. thus, the current loop compensation zero is: the total compensation capacitance is calculated: the value of the noise filtering capacitor is: the value of c ic is: the value of r ic is: select the r c value from the standard value, we have: r ic = 30k , c ic = 6.8nf, c ip = 1nf. figure 17 shows the actual bode plot of current loop gain. figure 16. asymptotic bode plot for current loop gain 10 100 -40 -20 0 20 40 60 80 100 120 frequency (hz) gain (db) f p f z 1k 10k 100k g iloop (s) f c gsm gid (s) gci (s) f z 1 2 ? r ic c ? ic ? ----------------------------------- - = (eq. 46) f p 1 2 ? r ic c ip c ? ic c ip c ic + ----------------------- - ? ? --------------------------------------------------- = (eq. 47) g id s ?? v out l bst s ? --------------------- - = (eq. 48) g ci s ?? gmi 1 c ic c ip + ?? s ? ------------------------------------ s 2 ? f z ?? ---------------------- 1 + s 2 ? f p ?? ---------------------- - 1 + -------------------------------- - ? = (eq. 49) gsm rcs rsen -------------- - ris 2 --------- 1 vm -------- - ? = (eq. 50) g iloop s ?? g id s ?? g sm g ci ? ? s ?? = (eq. 51) f z f c f c f p ------- ?? ?? ?? atan ? m + ?? ?? ?? tan -------------------------------------------------------- = (eq. 52) f z 14khz 14khz 6khz ----------------- - ?? ?? atan 20deg + ?? ?? tan --------------------------------------------------------------- ------------ - = 0.78khz = (eq. 53) c ip c ic v out l bst 2 ? f c ?? 2 ? -------------------------------------- - a idc v m ------------- - r cs r sen --------------- - ?? ?? ?? ?? 1f c f z ? ?? 2 + 1f c f p ? ?? 2 + ------------------------------ - ? ?? ?? ?? ?? = + (eq. 54) c ip c ic 7.345nf = + (eq. 55) c ip c ip c ic + ?? f z f p ---- = (eq. 56) c ip 7.345nf 0.78khz 6hz ---------------------- - ? 0.958nf == (eq. 57) c ic 7.345nf 0.958nf C 6.378nf == (eq. 58) r ic 1 2 ? 0.78khz 6.378nf ?? ------------------------------------------------------------- - 31.85k ? == (eq. 59) 0 50 gain (db) 10 100 0 30 60 90 frequency (hz) phase () 45 60 1k 10k 100k figure 17. bode plot of the actual current loop gain 100 f p f z f p f z
isl6731a, isl6731b 17 fn8582.1 february 13, 2015 submit document feedback input voltage setting first, set the bo resistor divider gain, k bo according to equations 1 and 2 . assuming the converter starts at v line = 80v rms , then the bo resistor divider gain, k bo , should be: in this design, two 470k resistors in series are used for r in2 . therefore, r in1 is calculated: we choose r in1 = 5.76k , the actual k bo is calculated: negative input capacitor generation the isl6731a and isl6731b generate an equivalent negative capacitance at the input to cancel the input filter capacitance. thus, more input capacitors can be used without reducing the power factor. the input equivalent negative capacitance is a function of the current sensing gain, bo resistor divider gain and the compensation components. this equivalent negative capa citor cancels the input filter capacitor required for emi filtering. therefore, the displacement power factor significantly improves. for example, c f1 = 0.68f, c f2 = c f3 = 0.47f, using the low cost emi filter shown in figure 13 . when v line = 230vac, f line = 50hz, p o = 300w. assuming 95% efficiency under the above test condition, the resistive component of the line curre nt, which is in phase to voltage: the reactive current through the input capacitors: thus, the displacement power factor is: the reactive current generated by the equivalent negative capacitor is: with the equivalent negative capacitor, the total reactive current reduces to: the displacement power factor increases to: voltage loop compensation the average boost diode forward current can be approximated by: assuming the input current traces the input voltage perfectly. the input power is in proportion to (v comp - 1v). where ? comp is the v comp - 1v. 1v is the offset voltage. r is is the internal current scaling resistor. r is = 14.2k . thus, the transfer function from v comp to v out is: as shown in figure 18 , the voltage loop gain is: k bo 0.5v 80v 2v C ------------------------ 0.00641 == (eq. 60) r in1 0.00641 1 0.00641 C ------------------------------ - 0.94m ? ?? ? 6.065k ? == (eq. 61) k bo r in1 r in1 r in2 + -------------------------------- - 0.00609 == (eq. 62) c neg k bo 0.8 v m v out --------------- - C ? ?? ?? ?? r sen r cs a idc ------------------------- - c ic c ip + ?? = (eq. 63) c neg 0.00609 0.8 1.5 390 --------- - C ? ?? ?? 3k 0.073 1.9 ? --------------------------- 6.8nf 1nf + ?? = 0.17 ? f = (eq. 64) i a p o v line 0.95 ? -------------------------------- - = 1.373a = (eq. 65) i c v line 2 ? f line ? ?? ? c f1 c f2 c f3 ++ ?? ? = 0.14a = (eq. 66) pf dis i a i a ?? 2 i c ?? 2 + ----------------------------------- = 0.9948 = (eq. 67) i cneg v line 2 ? f line ? ?? ? c neg ?? ? = 0.015a = (eq. 68) i c i cneg C 0.126a = (eq. 69) pf dis i a i a ?? 2 i c i cneg C ?? 2 + ------------------------------------------------------- - = 0.9958 = (eq. 70) i dave ?? p in v out --------------- - = (eq. 71) i dave ?? r sen r cs 0.5 r ? is ? --------------------------------------- 1 v out --------------- - ? 0.25 22 ??? ? ?? 2 k bo ? ----------------------------------------------- - ?? ?? ?? ?? ? comp ? ? = (eq. 72) i dave ?? 0.749 a v --- - ? comp ? = (eq. 73) fb comp gmv i fb 2.5v r fb1 r fb2 vout figure 18. output voltage sensing and compensation rvc cvc cvp g ps s ?? v out s ?? ? comp ----------------------- - = 1 c o s ? --------------- - i dave ?? ? comp -------------------- ? = (eq. 74) g ps s ?? i dave ?? c o s ? ------------------- 1 ? comp -------------------- ? ?? ?? ?? = 0.749 c o s ? --------------- - = (eq. 75) g vloop s ?? g ps s ?? g div gmv z comp ? ? ? s ?? = (eq. 76)
isl6731a, isl6731b 18 fn8582.1 february 13, 2015 submit document feedback the output feedback resistor divider gain, g div is: the compensation gain uses external impedance networks as shown in figure 18 , z comp (s) is given by: the targeted crossover frequency, f cv is 7.5hz. the high frequency pole, f pv , is required in order to reject the 2 time line frequency component. f pv = 20hz. the targeted phase margin is 50. the zero, f zv is calculated: then the total capacitance used for compensation is calculated: thus, the total compensation capacitance is: choose components from the standard values. we have c vp = 150nf, c vc = 1f, r vc = 62k . the actual bode plot is shown in figure 20 . g div v ref v out --------------- - = (eq. 77) z comp s ?? 1 c vc c vp + ?? s ? -------------------------------------- - r vc c vc s1 + ? ? r vc c vc ? c vp ? c vc c vp + ----------------------------------------- - s ? 1 + ------------------------------------------------------------ - ? = (eq. 78) figure 19. asymptotic bode plot of voltage loop gain 1 100 -60 -40 -20 0 20 40 60 frequency (hz) gain (db) f pv f zv 1k gmv*z comp (s) f cv gps (s) g vloop (s) 10 g div f zv f cv ? m f cv f pv ?? ? ?? atan + ?? tan --------------------------------------------------------------- --------------- - = (eq. 79) f zv 7.5hz 50deg 7.5hz ?? 20hz ?? ? ?? atan + ?? tan --------------------------------------------------------------- -------------------------------------- 2.648hz == (eq. 80) c vc c vp + g ps i2 ? f cv ?? ? ?? g div gmv ? ? 2 ? f cv ?? --------------------------------------------------------------- --------------------------- - f cv f zv ? ?? 2 1 + f cv f pv ? ?? 2 1 + -------------------------------------------- ? = (eq. 81) c vc c vp + 1127nf = (eq. 82) c vp 1127nf f zv f pv ---------- - ? 149nf == (eq. 83) c vc 1127nf 149.1nf C 977nf == (eq. 84) r vc 1 2 ? f zv c vc ?? ? ------------------------------------------ - 61.5k ? == (eq. 85) figure 20. bode plot of the actual voltage loop gain gain (db) frequency (hz) phase () -20 0 20 40 f cv 120hz 1 10 100 0 30 60 90 f cv 1k 120hz 0 45 60
isl6731a, isl6731b 19 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8582.1 february 13, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change february 13, 2015 fn8582.1 recommended operatin g conditions on page 7: changed vcc to gn d value from ?15v to +20v ?to ?12v to +20v?. updated equations 38 and 39 on page 15. march 25, 2014 fn8582.0 initial release
isl6731a, isl6731b 20 fn8582.1 february 13, 2015 submit document feedback package outline drawing m14.15 14 lead narrow body small outline plastic package rev 1, 10/09 a d 4 0.25 a-b mc c 0.10 c 5 b d 3 0.10 a-b c 4 0.20 c 2x 2x 0.10 d c 2x h 0.10 c 6 3 6 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 1.27 0.31-0.51 4 4 detail"a" 0.220.03 0.10-0.25 1.25 min 1.75 max (1.27) (0.6) 6.0 8.65 3.9 7 14 8 dimensioning and tolerancing conform to amsey14.5m-1994. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. interlead flash or protrusions shall not exceed 0.25mm per side . datums a and b to be determined at datum h. 4. 5. 3. 2. dimensions are in millimeters. notes: 1. the pin #1 indentifier may be either a mold or mark feature. 6. does not include dambar protrusion. allowable dambar protrusi on 7. reference to jedec ms-012-ab. shall be 0.10mm total in excess of lead width at maximum condit ion. detail "a" side view typical recommended land pattern top view

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